This invention relates to an apparatus and method for testing batch formed microelectronic devices to determine whether or not the batch forming methodology has been effectively carried out.
Microelectronic circuit devices are typically batch formed by, for example, discretizing the locations and geometry of said devices in an essentially continuous layer of semiconductor material and thereafter exposing the discretized semiconductor material to a forming medium which removes material from the semiconductor layer except where it is protected by an etchant resistant material commonly called xe2x80x9cphotoresist.xe2x80x9d A representative forming process is known as inductively coupled plasma deep reactive ion etching (ICP DRIE) in which the forming medium is a reactive plasma. Removal of the semiconductor material by the etchant is essentially a trenching process which begins on one surface of the semiconductor material and progresses through the material at a rate which is dependent upon a number of factors, including the width of the trench. The fact that the etch process progresses at different rates for different gap widths is a phenomenon known as xe2x80x9cetch lagxe2x80x9d and must be addressed any time devices with different gap widths in their geometry are to be formed in a batch forming process such as ICP DRIE.
One environment in which the etch lag phenomenon is encountered is in the batch forming of micro-electro-mechanical systems commonly referred to as MEMS. MEMS devices include, by way of example, micro-mechanical filters, pressure sensors, gyroscopes, resonators, actuators, rate sensors, and accelerometers. A typical MEMS device is fabricated in large numbers by batch etching a semiconductor layer. The geometry of MEMS devices is typically such that a reasonably high level of accuracy is needed in maintaining the proper trench widths or gap sizes between the structural elements thereof so that electrical and/or mechanical interactions or effects between adjacent semiconductor structures are within acceptable levels. It is particularly important that adjacent semiconductor structures which are separated and electrically isolated from one another by a minimum width gap are in fact fully formed; i.e., it is important that the trench which forms the gap is etched through the appropriate semiconductor layer so that a short circuit does not occur between the two adjacent semiconductor structures, and so that mechanical structures are completely separated. Because of the etch lag phenomenon described above, it is possible in a batch etching process that the wider isolation gaps will be fully formed while narrower structural trenches in the device are not fully formed and that electrical short circuits or mechanical connections as described above will occur.
Many MEMS devices involve etch trenching or gap formation through a portion of semiconductor material which is suspended in part over a cavity so as to create the potential for physical movement between closely adjacent portions of the semiconductor structure. By way of example, an accelerometer may require the semiconductor layer at each device location to be etched in such a way as to form a linear or radially disposed array of essentially parallel narrow fingers of semiconductor material which are supported at one end, for example, on an oxide base but which extend from the oxide base out over a cavity in a cantilevered fashion. The structure of such a device is described in greater detail in the related application identified above, the disclosure of which is incorporated herein by reference.
Where a number of long parallel trenches are to be etched through the semiconductor material over a cavity, another phenomenon can affect the electrical properties of the semiconductor structures formed by etching. To explain, a wide trench designed for either electrical or structural isolation may form earlier than nearby narrow trenches in the etch process as a result of the etch lag phenomenon described above. Once the wider trench is fully formed, the etchant can fill the cavity and, because it is highly active, begin eroding the bottoms of the long fingers of semiconductor material which overlie the cavity. This undesirable etch can change finger bottom geometry from a relatively thick rectangular structure to one which begins to resemble a knife-edge, i.e., the edges of the fingers at or near the bottoms begin to erode inwardly from the corners. As this erosion continues, the electrical resistance of a finger of semiconductor material increases while the capacitive coupling between adjacent fingers may decrease.
In the past it has been customary to evaluate the qualities of the individual semiconductor devices and particularly their electrical characteristics by sacrificing an entire semiconductor wafer. To explain, wafers may be drawn at random from the manufacturing process and cut through so as to be prepared for either visual or machine assisted inspection. While this is wasteful of materials and manufacturing efficiency, it is preferable to separating the devices from the etched wafer and installing them in individual packages which are later found to be faulty.
According to the present invention, electronic devices such as, but not limited to, MEMS which are batch formed from an essentially continuous layer of semiconductor material may be tested to evaluate the effectiveness of the batch forming medium without sacrificing entire wafers.
In general this is accomplished through the steps of:
A. forming electrical test probe contacts in test sites;
B. discretizing, such as by application of a photoresist pattern layer, the locations and geometry of the devices in the semiconductor material layer wherein the geometry includes the definition of one or more gaps in the material layer which affect the electrical and/or mechanical properties of the devices;
C. discretizing one or more test sites in the semiconductor layer so as to include at least one gap which is dimensionally representative of a gap in the device geometry; thereafter
D. subjecting the layer to the forming medium; and
E. measuring at least one electrical property associated with the test site gap by probing the contacts described above.
The term xe2x80x9cdiscretizingxe2x80x9d, as used herein, typically refers to the application and selective removal of photoresist to a surface of the semiconductor layer prior to exposing the layer to the etchant thereby to define those areas of the semiconductor layer where the etchant will trench through the material from the exposed side toward the other side. While this is the typical definition, Applicants intend this term to cover any and all known and future developed methods for creating the two-dimensional pattern which is ultimately desired in the semiconductor structure.
Furthermore, it is to be understood that, according to the present invention, steps (A), (B), and (C) can be performed in any desired order before performing step (D).
The method of the present invention can be applied as hereinafter described to the manufacture of MEMS devices in large quantities in wafers or sheets of semiconductor material which are fully bonded to a substrate as well as wafers or sheets which have cavities formed beneath the semiconductor layer. The test probe contacts may be arranged so as to permit the testing in the test sites of either or both of capacitance and resistance.
In one embodiment hereinafter described, the test site comprises a linear array of contacts separated by test site gaps which vary from one another in a systematic way; e.g., the gaps vary in width from one another by a fixed difference increment and define a range from a minimum value which is at or below the minimum gap width to a maximum value which is at or in excess of an isolation gap width such that the gaps in the devices to be batch formed all fall within the test site range whether or not they correspond exactly to any of the gap values in the range. Alternatively the gaps in the test site may be selected to correspond identically with the manufactured device gaps; the differences between these two approaches being a matter of individual preference. In the linear array, the gaps which are defined in the discretizing step; i.e., the application and selective removal of the photoresist pattern, are separated by untrenched, unetched semiconductor blocks and the entire linear array of blocks is separated from the rest of the semiconductor layer by way of an isolation gap defined in the discretizing step. Each of the blocks is preferably provided with a metalized layer which serves as a test probe contact. After the wafer has been etched, the test probe contacts may be accessed by suitable probes and the capacitance and resistance between contacts measured as an indication of the effectiveness of the etch process in the formation of other structures in the semiconductor layer which structures include geometry; i.e., trench widths, which correspond to or are represented by the linear gap array in the test site. In short, the test site acts as the representative of the entire wafer and the accuracy of this representation is assured by the fact that all areas of the wafer are etched at the same time.
The test site or sites may be strategically located throughout the device array or, where the value of surface area in the array is high, located in or along scribe streets or lines which will ultimately be used to separate devices from one another prior to further assembly steps. The test sites themselves perform no function after the test has been carried out and may be destroyed without loss.
Another embodiment of the invention, most advantageously applied in the testing of MEMS devices, involves a test site having long fingers of semiconductor structure formed in part over a cavity to both evaluate the trench formation as well as to characterize the long semiconductor structures to determine, for example, that they have not become excessively electrically resistive through undesirable etching as described above. In this embodiment, the test site is discretized in such a way as to create a geometry of long, narrow parallel fingers which partially overlie a cavity, which are separated by gaps of selected widths and which are implemented with probe contacts at the opposite supported ends thereof, i.e., the ends which overlie the substrate. In addition, leads are brought out from the test probe contacts in such a way as to facilitate the application of test probe electronics to the leads for evaluation not only of inter-digital capacitance, i.e., the capacitance across the various gaps, but also to quantify and/or measure for acceptability of the resistance of the individual fingers. Again, the geometry of the test site is chosen to be representative of the devices themselves in the wafer in which a numerically large array of devices is simultaneously formed along with the test sites.
As in the first embodiment, the test sites may be located in or along scribe lines where they will not reduce the manufacturing: efficiency measured as a function of the utilization of wafer area.
In either or both of the embodiments, the probe contacts can be and preferably are interconnected with leads which themselves are geometrically arranged in a standardized fashion so that a single probe card may be designed for application to either or both of the first and second embodiment arrangements described above. It is not uncommon to advantageously use both the linear trench width test site monitoring array and the finger etch embodiments on a single wafer for multiple test purposes.
Advantages and applications of the present invention will become apparent to those skilled in the art when the detailed description of the best mode contemplated for practicing the invention, as set forth hereinbelow, is read in conjunction with the accompanying drawings.